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| QL5632 Enhanced QuickPCI Device Data Sheet ****** 34 33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM * Reference design with driver code (Win PCI Bus 33 MHz/32 bits (data and address) * * * * * * * * Master Controller High Speed Data Path Target Controller 32 bit Interface Programmable Logic Config space High Speed Logic Cells DMA Controller 95/98/Win 2000/NT4.0) available PCI v2.3 compliant Supports Type 0 Configuration Cycles in Target mode 3.3 V PCI signaling 2.5 V Supply Voltage 280-ball LFBGA 208-pin PQFP Supports Extendable PCI functionality Unlimited/Continuous Burst Transfers supported 115/51 User I/O 160 MHz FIFOs PCI Bus Extendable PCI Functionality * Support for PCI host-bridge function * Support for Configuration Space from 0 x 40 to 0 x 3FF * Multi-Function, Expanded Capabilities, and Figure 1: QL5632 Diagram Device Highlights High Performance PCI Controller * 32-bit / 33 MHz PCI Master/Target * Zero-wait state PCI Master provides * * * * * * * * Expansion ROM capable * PCI v2.3 Power Management Spec compatible * PCI v2.3 Vital Product Data (VPD) configuration support 132 MBps transfer rates Zero-wait-state PCI Target Write/One-waitstate PCI Target Read interface Supports all PCI commands, including configuration and MWI Supports fully-customizable byte enable for master channels Target interface supports retry, disconnect with/without data transfer, and target abort Fully programmable back-end interface Independent PCI bus (33 MHz) and local bus (up to 160 MHz) clocks Fully customizable PCI Configuration Space Configurable FIFOs with depths up to 256 words Flexible Programmable Logic 772 Logic Cells 41,472 RAM bits Up to 115 I/O pins All back-end interface and glue-logic can be implemented on chip * Six 32-bit busses interface between the PCI Controller and the Programmable Logic * Eighteen 2,304 bit Dual Port High Performance SRAM Blocks * 1,889 flip-flops available * * * * (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 1 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Architecture Overview The QL6432 device in the QuickLogic QuickPCI ESP (Embedded Standard Product) family provides a complete and customizable PCI interface solution combined with programmable logic. This device eliminates any need for the designer to worry about PCI bus compliance, yet allows for the maximum 32-bit PCI bus bandwidth (132 MBps). The programmable logic portion of the device contains 772 QuickLogic Logic Cells and 18 QuickLogic Dual-Port RAM Blocks. These configurable RAM blocks can be configured in many width/depth combinations. They can also be combined with logic cells to form FIFOs, or be initialized via Serial EEPROM on power-up and used as ROMs. The QL6432 device meets PCI 2.3 electrical and timing specifications and has been fully hardware-tested. This device also supports the Win'98 and PC'98 standards. The QL6432 device features 2.5 V operation with multi-volt compatible I/Os. The device can easily operate in 3 V embedded systems and is fully compatible with 3.3 V applications. PCI Controller The PCI Controller is a 32-bit/33 MHz PCI 2.3 Compliant Master/Target Controller capable of infinite length Master Write and Read transactions at zero wait states (132 MBps). The Master will never insert wait states during transfers, so data is supplied or received by FIFOs that can be configured in the programmable region of the device. The Master is capable of initiating any type of PCI commands, including configuration cycles and Memory Write and Invalidate (MWI). This enables the QL6432 device to act as a PCI host. The Master Controller will most often be operated by a DMA Controller in the programmable region of the device. DMA Controller reference design is available and will be included in the QuickWorks 9.3 design software. The Target interface offers full PCI Configuration Space and flexible target addressing. It supports zero-wait-state target Write and one-wait-state target Read operations. It also supports retry, disconnect with/without data transfer, and target abort requested by the back end. Any number of 32-bit BARs may be configured as either memory or I/O space. All required and optional PCI 2.3 Configuration Space registers can be implemented within the programmable region of the device. A reference design of a Target Configuration and Addressing module is available and will be included in the QuickWorks 9.3 design software. The interface ports are divided into a set of ports for master transactions and a set for target transactions. The Master DMA controller and Target Configuration Space and Address Decoding are done in the programmable logic region of the device. These functions are not timing critical, so leaving these elements in the programmable region allows the greatest degree of flexibility to the designer. Reference DMA controller, Configuration Space, and Address Decoding blocks are readily available so that the design cycle can be minimized. 2 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Configuration Space and Address Decode The configuration space is completely customizable in the programmable region of the device. PCI address and command decoding is performed by logic in the programmable section of the device. This allows support for any size of memory or I/O space for back end logic. It also allows the user to implement any subset of the PCI commands supported by the QL6432. In the reference design, QuickLogic provides a reference Address Register/Counter and Command Decode block. DMA Master Target Controller The customizable DMA controller included with the QuickWorks design software contains the following features: * Configurable DMA count size for Reads and Writes (up to 30 bits) * Configurable DMA burst size for PCI (including unlimited/continuous burst) * Customizable PCI command to use by core * Customizable Byte Enable signal * Programmable Arbitration between DMA Read & Write transactions * DMA Registers may be mapped to any area of Target Memory Space, including: * Read Address (32-bit register) * Write Address (32-bit register) * Read Length (16-bit register) / Write Length (16-bit register) * Control and Status (32-bit register, includes 8 bit Burst Length) * DMA Registers are available to the local design or the PCI bus * Programmable Interrupt Control to signal end of transfer or other event (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 3 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Configurable FIFOs FIFOs may be created with the RAM/FIFO wizard in the QuickWorks tools. Figure 2 shows the graphical interface used to create these FIFOs. FIFOs may be designed up to 1,889 words deep. The 18 RAM cells available in the QL6432 allow for up to: * 9 FIFOs at 128 words deep (36 wide) * 4 FIFOs at 256 words deep (36 wide) * 2 FIFOs at 512 words deep (36 wide) * 1 FIFO at 1,024 words deep (36 wide) Figure 2: Graphical Interface to create FIFO PCI Interface Symbol Figure 3 shows the interface symbol you have to use in your schematic design in order to attach the local interface programmable logic design to the PCI core. If you are designing with a toplevel Verilog or VHDL file you must use a structural instantiation of this PCI32_25um block instead of a graphical symbol. 4 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Figure 3: PCI Interface (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 5 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C PCI Master Interface The internal signals used to interface with the PCI controller in the QL6432 are listed in Table 10 along with a description of each signal. The direction of the signal indicates if the signal is an input provided by the local interface (I) or an output provided by the PCI controller (O). NOTE: Signals that end with the character `N' should be considered active-low (for example, Mst_IRDYN). Table 10: PCI Master Interface Signal Type Description PCI command to be used for the master transaction This signal must remain unchanged throughout the period when Mst_Burst_Req is active. PCI commands considered as reads include Interrupt Acknowledge, I/O Read, Memory Read, Configuration Read, Memory Read Multiple, Memory Read Line. PCI commands considered as writes include Special Cycle, I/O Write, Memory Write, Configuration Write, Memory Write and Invalidate. Users should make sure that only valid PCI commands are supplied. Request use of the PCI bus When this signal is active, the core requests the PCI bus and then generates a master transaction. This signal should be held active until all requested data are transferred on the PCI bus and deactivated in the 2nd clock cycle following the last data transfer on PCI (to avoid being considered as requesting a new transaction). Address for master DMA writes This address must be treated as valid from the beginning of a DMA Write until the DMA Write operation is complete. It should be incremented by 4 bytes each time data is transferred on the PCI bus. Address for master DMA reads This address must be treated as valid from the beginning of a DMA read until the DMA Read operation is complete. It should be incremented by 4 bytes each time data is transferred on the PCI bus. Data for master DMA Writes (to PCI bus) Byte enables for master DMA Reads and writes Active-low. Data and byte enable valid on Mst_WrData[31:0] (for master Write only) and Mst_BE[3:0] (for both master Read and Write) Data receive acknowledge for Mst_WrData[31:0] (for master Write only) and Mst_BE[3:0] (for both) This serves as the PUSH control for the internal FIFO and the POP control for the external FIFO (in FPGA region) which provides data and byte enables to the PCI32 core. Byte enable select for master transactions When low, Mst_BE[3:0] should remain constant throughout the entire transfer (when Mst_Burst_Req is active) and it is used for every data phase of the master transaction. When high, Mst_BE[3:0] pushed into internal FIFO (along with data in case of master Write) is used. Should be held constant throughout the transaction. Master Write transaction is completed Active for only one clock cycle. PCI_cmd[3:0] I mst_burst_req I mst_wrAd[31:0] I mst_rdAd[31:0] I Mst_WrData[31:0] Mst_BE[3:0] Mst_WrData_Valid I I I Mst_WrData_Rdy O Mst_BE_Sel I Mst_WrBurst_Done O 6 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Table 10: PCI Master Interface Signal Type Description Master Read termination mode select when Mst_BE_Sel is high When both Mst_BE_Sel and Mst_Rd_Term_Sel are high, master Read termination happens when the internal FIFO is empty, and Mst_Two_Reads and Mst_One_Read are ignored. When either signal is low, Mst_Two_Reads and Mst_One_Read are used to signal end of master Read. Should be held constant throughout the transaction. This signals to the PCI32 core that only one data transfer remains to be read in the burst Read. Two data transfers remain to be read in the burst Read It is not used for single-data-phase master read transactions. Master Read data valid on Usr_Addr_WrData[31:0] This serves as the PUSH control for the external FIFO (in FPGA region) that receives data from the PCI32 core. Master Read transaction is completed Active for only one clock cycle. Internal FIFO flush FIFO flushed immediately after it is active (synchronized with PCI clock). Enable Latency Counter Set to 0 to ignore the Latency Timer in the PCI configuration space (offset 0Ch). For full PCI compliance, this port should be always set to 1. Data was transferred on the previous PCI clock Useful for updating DMA transfer counts on DMA Read operations Active during the last data transfer of a master transaction Copy of the PCI REQN signal generated by QL5632 as PCI master Not usually used in the back-end design. Copy of the PCI IRDYN signal generated by QL5632 as PCI master Valid only when QL5 x 33 is the PCI master. Kept low otherwise. Not usually used in the back-end design. Target abort detected during master transaction This is normally an error condition to be handled in the DMA controller. Target timeout detected (no response from target) This is normally an error condition to be handled in the DMA controller. Mst_Rd_Term_Sel I Mst_One_Read Mst_Two_Reads I I Mst_RdData_Valid Mst_RdBurst_Done Flush_FIFO O O I Mst_LatCntEn I Mst_Xfer_D1 Mst_Last_Cycle Mst_REQN O O O Mst_IRDYN O Mst_Tabort_Det Mst_TTO_Det O O (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 7 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C PCI Target Interface Table 11: PCI Target Interface Signal Type Description Target address, and target Write data During all target accesses, the address is presented on Usr_Addr_WrData[31:0] at the same time Usr_Adr_Valid is active. During target Write transactions, this port also presents valid Write data to the PCI configuration space or user logic when Usr_Adr_Inc is active. PCI command and byte enables During target accesses, the PCI command is presented on Usr_CBE[3:0] at the same time Usr_Adr_Valid is active. This port also presents active-low byte enables to the PCI configuration space or user logic. Indicates the beginning of a PCI transaction, and that a target address is valid on Usr_Addr_WrData[31:0] and the PCI command is valid on Usr_CBE[3:0]. When this signal is active, the target address must be latched and decoded to determine if this address belongs to the device's memory or I/O space. Also, the PCI command must be decoded to determine the type of PCI transaction. On subsequent clocks of a target access, this signal is low, indicating that address is NOT present on Usr_Addr_WrData[31:0]. Indicates that the target address should be incremented, because the previous data transfer has been completed. During burst target accesses, the target address is only presented to the back-end logic at the beginning of the transaction (when Usr_Adr_Valid is active), and must therefore be latched and incremented by 4 for subsequent data transfers. Note that during target Write transactions, Usr_Adr_Inc indicates valid data on Usr_Addr_WrData[31:0] that must be accepted by the backend logic (regardless of the state of Usr_Rdy). During Read transactions, Usr_Adr_Inc signals to the backend that the PCI core has presented the read data on the PCI bus (TRDYN asserted). This signal should be the combinatorial decode of the "user read" command from Usr_CBE[3:0]. This command may be mapped from any of the PCI "read" commands, such as Memory Read, Memory Read Line, Memory Read Multiple, I/O Read, etc. It is internally gated with Usr_Adr_Valid. This signal should be the combinatorial decode of the "user write" command from Usr_CBE[3:0]. This command may be mapped from any of the PCI "write" commands, such as Memory Write or I/O Write. It is internally gated with Usr_Adr_Valid. This signal should be driven active when the address on Usr_Addr_WrData[31:0] has been decoded and determined to be within the address space of the device. Usr_Addr_WrData[31:0] must be compared to each of the valid Base Address Registers in the PCI configuration space. Also, this signal must be gated by the Memory Access Enable or I/O Access Enable registers in the PCI configuration space (Command Register bits 1 or 0 at offset 04h). Internally gated with Usr_Adr_Valid. Usr_Addr_WrData[31:0] O Usr_CBE[3:0] O Usr_Adr_Valid O Usr_Adr_Inc O Usr_RdDecode I Usr_WrDecode I Usr_Select I 8 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Table 11: PCI Target Interface (Continued) Signal Type Description This signal is active throughout a "user write" transaction, which has been decoded by Usr_WrDecode at the beginning of the transaction. The Write strobe for individual DWORDs of data (on Usr_Addr_WrData[31:0]) during a user Write transaction should be generated by logically ANDing this signal with Usr_Adr_Inc. This signal is active throughout a "configuration write" transaction. The Write strobe for individual DWORDs of data (on Usr_Addr_WrData[31:0]) during a configuration Write transaction should be generated by logically ANDing this signal with Usr_Adr_Inc. This signal is active throughout a "user read" transaction, which has been decoded by Usr_RdDecode at the beginning of the transaction. This signal is active throughout a "configuration read" transaction. Data from the PCI configuration registers, required to be presented during PCI configuration reads. Data from the back-end user logic, required to be presented during PCI user reads. Bits 3 from the Command Register in the PCI configuration space (offset 04h). Enable Special Cycle monitoring. If high, the core reports data parity error in Special Cycles through SERRN if Cfg_CmdReg8 is active. Bits 4 from the Command Register in the PCI configuration space (offset 04h). Memory Write and Invalidate (MWI) Enable. If high, the core generates MWI transactions as requested by the backend. Otherwise it uses Memory Write instead even if MWI is requested. Bits 6 from the Command Register in the PCI configuration space (offset 04h). Parity Error Response. If high, the core uses PERRN to report data parity errors. Otherwise it never drives it. Bits 8 from the Command Register in the PCI configuration space (offset 04h). SERRN Enable. If high, the cores uses SERRN to report address parity errors if Cfg_CmdReg6 is high. 8-bit value of the Latency Timer in the PCI configuration space (offset 0Ch). Used when a target read operation should return the value set on the Mst_RdAd[31:0] pins. This select pin saves on logic which would otherwise need to be used to multiplex Mst_RdAd[31:0] into the Usr_RdData[31:0] bus. When this signal is asserted, the data on Usr_RdData[31:0] is ignored. Used when a target read operation should return the value set on the Mst_WrAd[31:0] pins. This select pin saves on logic which would otherwise need to be used to multiplex Mst_WrAd[31:0] into the Usr_RdData[31:0] bus. When this signal is asserted, the data on Usr_RdData[31:0] is ignored. Parity error detected on the PCI bus. When this signal is active, bit 15 of the Status Register must be set in the PCI configuration space (offset 04h). Usr_Write O Cfg_Write O Usr_Read Cfg_Read Cfg_RdData[31:0] Usr_RdData[31:0] O O I I Cfg_CmdReg3 I Cfg_CmdReg4 I Cfg_CmdReg6 I Cfg_CmdReg8 I Cfg_LatCnt[7:0] I Usr_MstRdAd_Sel I Usr_MstWrAd_Sel I Cfg_PERR_Det O (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 9 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Table 11: PCI Target Interface (Continued) Signal Cfg_SERR_Sig Type O Description System error asserted on the PCI bus. When this signal is active, the Signalled System Error bit, bit 14 of the Status Register, must be set in the PCI configuration space (offset 04h). Data parity error detected on the PCI bus by the master. When this signal is active, bit 8 of the Status Register must be set in the PCI configuration space (offset 04h). Inverted copy of the TRDYN signal as driven by the PCI target interface. Valid only within a target access. Inverted copy of the STOPN signal as driven by the PCI target interface. Valid only within a target access. Inverted copy of the DEVSELN signal as driven by the PCI target interface. Valid only within a target access. Active one clock cycle after the last data phase (may not with data transfer) occurs on PCI and inactive one clock cycle afterwards. Used to delay (add wait states to) a target PCI transaction when the backend needs additional time to provide data (read) or accept data (write). Subject to PCI latency restrictions. Used to prematurely stop a PCI target access on the next PCI clock. Used to signal Target Abort on PCI when the backend has fatal error and is unable to complete a transaction. Rarely used. Cfg_MstPERR_Det O Usr_TRDY Usr_STOPO Usr_DEVSEL Usr_Last_Cycle_D1 O O O O Usr_Rdy Usr_Stop Usr_Abort I I I PCI Internal Signals Table 12: PCI Internal Signal Signal PCI_clock PCI_reset PCI_IRDYN_D1 PCI_FRAMEN_D1 PCI_DEVSELN_D1 PCI_TRDYN_D1 PCI_STOPN_D1 PCI_IDSEL_D1 Type O O O O O O O O Description PCI clock. PCI reset signal. Copy of the IRDYN signal from the PCI bus, delayed by one clock. Copy of the FRAMEN signal from the PCI bus, delayed by one clock. Copy of the DEVSELN signal from the PCI bus, delayed by one clock. Copy of the TRDYN signal from the PCI bus, delayed by one clock. Copy of the STOPN signal from the PCI bus, delayed by one clock. Copy of the IDSEL signal from the PCI bus, delayed by one clock. 10 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C RAM Module Features The QL6432 device has eighteen 2,304-bit RAM modules, for a total of 41,472 RAM bits. Using two "mode" pins, designers can configure each module into 128 x 18, 256 x 9, 512 x 4, or 1024 x 2 blocks (see Figure 1). The blocks are also easily cascadable to increase their effective width or depth. The RAM modules are "dual-ported" with completely independent Read and Write ports and separate Read and Write clocks. The Read ports support asynchronous and synchronous operation, while the Write ports support synchronous operation. Each port has 18 data lines and 10 address lines, allowing word lengths of up to 18 bits and address spaces of up to 1,024 words. Depending on the mode selected, however, some higher order data or address lines may not be used. The Write Enable (WE) line acts as a clock enable for synchronous Write operation. The Read Enable (RE) acts as a clock enable for synchronous Read operation (ASYNCRD input low), or as a flow-through enable for asynchronous Read operation (ASYNCRD input high). Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. This approach allows up to 1,024-deep configurations as large as 44 bits wide in the QL6432 device. A similar technique can be used to create depths greater than 1,024 words. In this case, address signals higher than the eighth bit are encoded onto the write enable (WE) input for Write operations. The Read data outputs are multiplexed together using encoded higher Read address bits for the multiplexer SELECT signals. [9:0] [17:0] WA WD WE WCLK RE RCLK RA RD ASYNCRD [9:0] [17:0] [1:0] MODE QuickRAM Module Figure 4: RAM Module (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 11 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Embedded Computational Unit (ECU) Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively--these functions require high logic cell usage while garnering only moderate performance results. The QL5632 architecture allows for functionality above and beyond that achievable using programmable logic devices. By embedding a dynamically reconfigurable computational unit, the QL5632 device can address various arithmetic functions efficiently. This approach offers greater performance than traditional programmable logic implementations. The embedded block is implemented at the transistor level as shown in Figure 5. RESET D S1 S2 S3 CIN SIGN1 SIGN2 00 01 3-1 mux 10 Q[0 3-4 decoder C B A A[0:7] A[8:15] 8-bit Multiplier 2-1 mux 16-bit Adder D Q 17 inc. 17-bit COUT Register A[0:15] CLK B[0:15] 2-1 mux Figure 5: ECU Block Diagram The 10 QL5632 ECU blocks are placed next to the SRAM circuitry for efficient memory/instruction fetch and addressing for DSP algorithmic implementations. Ten 8-bit MAC functions can be implemented per cycle for a total of ~1 billion MACs/s when clocked at 98 MHz. Additional multiply-accumulate functions can be implemented in the programmable logic. 12 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C The modes for the ECU block are dynamically re-programmable through the programmable logic. Table 13: ECU Mode Select Criteria Instruction Operation S1 0 0 0 0 1 1 1 1 S2 0 0 1 1 0 0 1 1 S3 0 1 0 1 0 1 0 1 Multiply Multiply-Add Accumulate Add Multiply (registered) c b ECU Performancea, t -B WCC t PD t SU CO 7.0 ns max 9.4 ns max 4.1 ns min 3.3 max 10.2 ns min 10.2 ns min 10.2 ns min 4.1 ns min 1.2 ns max 1.2 ns max 1.2 ns max 1.2 ns max 1.2 ns max Multiply- Add (registered) Multiply - Accumulate Add (registered) a. tPD, tSU and tCO do not include routing paths in/out of the ECU block. b. Internal feedback path in ECU restricts max clk frequency to 224 MHz. c. B [15:0] set to zero. NOTE: Timing numbers in Table 13 represent -B Worst Case Commercial conditions. PLLs Instead of requiring extra components, designers simply need to instantiate one of the preconfigured models (described in this section). The QuickLogic built-in PLLs support a wider range of frequencies than many other PLLs. These PLLs also have the ability to be cascaded to support different ranges of frequency multiplications or divisions, driving the device at a faster or slower rate than the incoming clock frequency. Most importantly, they achieve a very short clock-to-out time--generally less than 3 ns. This low clock-to-out time is achieved by the Phase Locked Loop subtracting the clock tree delay through the feedback path, effectively making the clock tree delay zero. Figure 6 illustrates a typical QuickLogic ESP PLL. (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 13 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C 1st Quadrant 2nd Quadrant 3rd Quadrant FIN Frequency Divide _ .1 . . _2 . . _4 . + Filter vco PLL Bypass 4th Quadrant Clock Tree Frequency Multiply . _1 . . _2 . . _4 . FOUT Figure 6: PLL Block Diagram Fin represents a very stable high-frequency input clock and produces an accurate signal reference. This signal can either bypass the PLL entirely, thus entering the clock tree directly, or it can pass through the PLL itself. Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external Fin signal and the local VCO form a control loop. The VCO is multiplied or divided down to the reference frequency, so that a phase detector (the crossed circle in Figure 6) can compare the two signals. If the phases of the external and local signals are not within the tolerance required, the phase detector sends a signal through the charge pump and loop filter (Figure 6). The charge pump generates an error voltage to bring the VCO back into alignment, and the loop filter removes any high frequency noise before the error voltage enters the VCO. This new VCO signal enters the clock tree to drive the chip's circuitry. Fout represents the clock signal emerging from the output pad (the output signal PLLPAD_OUT is explained in Table 15). This clock signal is meaningful only when the PLL is configured for external use; otherwise, it remains in high Z state, as shown in the post-simulation waveform. Most QuickLogic products contain four PLLs, one to be used in each quadrant. The PLL presented in Figure 6 controls the clock tree in the fourth Quadrant of its ESP. QuickLogic PLLs compensate for the additional delay created by the clock tree itself, as previously noted, by subtracting the clock tree delay through the feedback path. For more specific information on the Phase Locked Loops, please refer to QuickLogic Application Note 58. 14 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C PLL Modes of Operation QuickLogic PLLs have eight modes of operation, based on the input frequency and desired output frequency--Table 14 indicates the features of each mode. NOTE: "HF" stands for "high frequency" and "LF" stands for "low frequency." Table 14: PLL Mode Frequencies PLL Model PLL_HF PLL_LF PLL_MULT2HF PLL_MULT2LF PLL_DIV2HF PLL_DIV2LF PLL_MULT4 PLL_DIV4 Output Frequency Same as input Same as input 2x 2x 1/2x 1/2x 4x 1/4x Input Frequency Range 66 MHz-150 MHz 25 MHz-133 MHz 50 MHz-125 MHz 16 MHz-50 MHz 100 MHz-250 MHz 50 MHz-100 MHz 16 MHz-40 MHz 100 MHz-300 MHz Output Frequency Range 66 MHz-150 MHz 25 MHz-133 MHz 100 MHz-250 MHz 32 MHz-100 MHz 50 MHz-125 MHz 25 MHz-50 MHz 64 MHz-160 MHz 25 MHz-75 MHz NOTE: The input frequency can range from 16 MHz to 300 MHz, while output frequency ranges from 25 MHz to 250 MHz. When you add PLLs to your top-level design, be sure that the PLL mode matches your desired input and output frequencies. PLL Signals Table 15 summarizes the key signals in QuickLogic's PLLs. Table 15: PLL Signals Signal Name PLLCLK_IN PLL_RESET Input clock signal Active High Reset If PLL_RESET is asserted, then CLKNET_OUT and PLLPAD_OUT are reset to 0. This signal must be asserted and then released in order for the LOCK_DETECT to work. PLL output This signal selects whether the PLL will drive the internal clock network or be used off-chip. This is a static signal, not a dynamic signal. Tied to GND = outgoing signal drives internal gates. Tied to VCC = outgoing signal used off-chip. Out to internal gates This signal bypasses the PLL logic before driving the internal gates. Note that this signal cannot be used in the same quadrant where the PLL signal is used (PLLCLK_OUT). Description ONn_OFFCHIP CLKNET_OUT (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 15 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Table 15: PLL Signals (Continued) Signal Name PLLCLK_OUT PLLPAD_OUT Description Out from PLL to internal gates This signal can drive the internal gates after going through the PLL. For this to work, ONn_OFFCHIP must be tied to GND. Out to off-chip This outgoing signal is used off-chip. For this to work, ONn_OFFCHIP signal must be tied to VCC. Active High Lock detection signal NOTE: For simulation purposes, this signal gets asserted after 10 clock cycles. However, it can take a maximum of 200 clock cycles to sync with the input clock upon release of the RESET signal. LOCK_DETECT NOTE: Because PLLCLK_IN and PLL_RESET signals have INPAD, and PLLPAD_OUT has OUTPAD, you do not have to add additional pads to your design. JTAG Support TCK TMS TRSTB TAp Controller State Machine (16 States) Instruction Decode & Control Logic Instruction Register RDI Mux Boundary-Scan Register (Data Register) Mux TDO Bypass Register Internal Register I/O Registers User Defined Data Register Figure 7: JTAG Block Diagram The Joint Test Access Group (JTAG) pins support the IEEE Standard 1149.1a to provide boundary scan capability for the QL6432 device. Six pins are dedicated to JTAG and programming functions on each QL6432 device; these pins are unavailable for general design input and output signals. TDI, TDO, TCK, TMS, and TRSTB are JTAG pins. The sixth pin, STM, is used only for programming. 16 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges. One of these challenges concerns the accessibility of test points. JTAG was formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR); these allow users to run three required tests, along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. The JTAG 1149.1 standard requires the following three tests: * Extest Instruction. The Extest instruction performs a PCB interconnect test. This test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. * Sample/Preload Instruction. This instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. * Bypass Instruction. The Bypass instruction allows data to skip a device's boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register connects the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device. Development Tool Support Software support for the QL6432 device is available through the QuickWorks development package. This turnkey PC-based QuickWorks package, shown in Figure 8, provides a complete ESP software solution with design entry, logic synthesis, place and route, and simulation. QuickWorks includes VHDL, Verilog, schematic, and mixed-mode entry with fast and efficient logic synthesis provided by the integrated Synplicity Synplify Lite tool which is specially tuned to take advantage of the QL6432 architecture. QuickWorks also provides functional and timing simulation for guaranteed timing and source-level debugging. The UNIX-based QuickTools package is a subset of QuickWorks and provides a solution for designers who use schematic-only design flow third-party tools for design entry, synthesis, or simulation. QuickTools Reads EDIF netlists and provides support for all QuickLogic devices. QuickTools also supports a wide range of third-party modeling and simulation tools. (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 17 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C QuickWorks Design Software Third Party Design Entry & Synthesis SCS Tools Mixed-Mode Design Schematic Verilog VHDL/ Turbo HDL Editor Synplify-Lite HDL Synthesis Simulator Third Party Simulation Optimize, Place, Route Silos III Aldec Figure 8: QuickWorks Tool Suite Electrical Specifications Table 16: Absolute Maximum Ratings Parameter VCC Voltage VCCIO Voltage VREF Voltage Input Voltage Value -0.5 V to 3.6 V -0.5 V to 4.6 V 2.7 V -0.5 V to VCCIO +0.5 V Parameter DC Input Current ESD Pad Protection Leaded Package Storage Temperature Laminate Package (BGA) Storage Temperature Value 20 mA 2000 V -65C to +150C -55C to +125C Table 17: Operating Range Military Symbol VCC VCCIO TA TJ K Parameter Min Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Junction Temperature Delay Factor -33B Speed Grade 0.42 2.3 2.3 -55 125 1.35 0.43 1.26 0.46 1.23 Max 2.7 3.6 Min 2.3 2.3 -40 Max 2.7 3.6 85 Min 2.3 2.3 0 Max 2.7 3.6 70 V V C C n/a Industrial Commercial Unit 18 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C DC Characteristics Table 18: DC Characteristics Temperature Symbol II IOZ CI IOS ICC ICCIO ICCIO(DIF) IREF IPD Parameter I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitance a Conditions Min VI = VCCIO or GND VI = VCCIO or GND b Unit Max 10 10 8 -180 210 2 2 10 150 A A pF mA mA mA mA mA A A -10 -10 -15 40 0.50 (typ) 0 -10 - Output Short Circuit Current Quiescent Current Quiescent Current on VCCIO Quiescent Current on VCCIO for Differential I/O Quiescent Current on VREF Vo = GND Vo = VCC VI,Vo = VCCIO or GND VCCIO = 3.6 V Pad Pull-down (programmable) a. Capacitance is sample tested only. Clock pins are 12 pF maximum. b. Only one output at a time. Duration should not exceed 30 seconds. Table 19: DC Input and Output Levels INREF VMIN LVTTL LVCMOS 2 GTL+ PCI SSTL2 SSTL3 n/a n/a 0.88 n/a 1.15 1.3 VMAX n/a n/a 1.12 n/a 1.35 1.7 VMIN -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 VIL VMAX 0.8 0.7 INREF - 0.2 0.3 x VCCIO INREF 0.18 INREF - 0.2 VMIN 2.0 1.7 INREF + 0.2 0.5 x VCCIO INREF + 0.18 INREF + 0.2 VIH VMAX VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.5 VCCIO + 0.3 VCCIO + 0.3 VOL VMAX 0.4 0.7 0.6 VOH VMIN 2.4 1.7 n/a IOL mA 2.0 2.0 40 IOH mA -2.0 -2.0 n/a -0.5 -7.6 -8 0.1 x VCCIO 0.9 x VCCIO 1.5 0.74 1.10 1.76 1.90 7.6 8 NOTE: The data provided in Table 19 are JEDEC and PCI Specifications--QuickLogic devices either meet or exceed these requirements. For data specific to QuickLogic I/Os, see Table 16 through Table 29 and Figure 9 through Figure 21. NOTE: All CLK and IOCTRL pins are clamped to the Vcc rail, not the Vccio. Therefore, these pins can only be driven up to Vcc + 0.3 V. (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 19 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C AC Characteristics The AC characteristics are calculated at 2.5 V, TA = 25C (K = 0.74). To calculate delays, multiply the appropriate K factor in Table 17 by the numbers presented in Table 20 through Table 27. Table 20: Logic Cells Symbol Parameter Logic Cells tPD tSU tHL tCO tCWHI tCWLO tSET tRESET tSW tRW Combinatorial Delay of the Longest Path: time taken by the combinatorial circuit to output Setup Time: time the synchronous input of the flip flop must be stable before the active clock edge Hold Time: time the synchronous input of the flip flop must be stable after the active clock edge Clock to Out Delay: the amount of time taken by the flip flop to output after the active clock edge. Clock High Time: required minimum time the clock stays high Clock Low Time: required minimum time that the clock stays low Set Delay: time between when the flip flop is "set" (high) and when the output is consequently "set" (high) Reset Delay: time between when the flip flop is "reset" (low) and when the output is consequently "reset" (low) Set Width: time that the SET signal remains high/low Reset Width: time that the RESET signal remains high/low Min 0.22 0 0.46 0.46 0.3 0.3 Max 0.257 0.255 0.18 0.09 Value (ns) SET D CLK RESET Q Figure 9: Logic Cell 20 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C CLK t (min) CWHI t (min) CWLO SET RESET Q t RESET t RW t SET t SW Figure 10: Logic Cell Flip Flop Timing - First Waveform CLK D tSU tHL Q tCO Figure 11: Logic Cell Flip Flop Timing - Second Waveform (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 21 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Table 21: RAM Cell Synchronous Write Timing Value (ns) Symbol tSWA tHWA tSWD tHWD tSWE tHWE tWCRD Parameter: RAM Cell Synchronous Write Timing Min WA setup time to WCLK: the amount of time the Write ADDRESS must be stable before the active edge of the Write CLOCK WA hold time to WCLK: the amount of time the Write ADDRESS must be stable after the active edge of the Write CLOCK WD setup time to WCLK: the amount of time the Write DATA must be stable before the active edge of the Write CLOCK WD hold time to WCLK: the amount of time the Write DATA must be stable after the active edge of the Write CLOCK WE setup time to WCLK: the amount of time the Write ENABLE must be stable before the active edge of the Write CLOCK WE hold time to WCLK: the amount of time the Write ENABLE must be stable after the active edge of the Write CLOCK WCLK to RD (WA=RA): the amount of time between the active Write CLOCK edge and the moment when the data is available at RD 0.675 0 0.654 0 0.623 0 - [9:0] [17:0] WA WD WE WCLK RE RCLK RA RD ASYNCRD [9:0] [17:0] [1:0] MODE RAM Module Figure 12: RAM Module 22 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C WCLK WA tSWA tHWA WD tSWD tHWD WE tSWE tHWE new data tWCRD RD old data Figure 13: RAM Cell Synchronous Write Timing RCLK RA t SRA t HRA RE t SRE t HRE new data RD old data t RCRD r PDRD Figure 14: RAM Cell Synchronous & Asynchronous Read Timing (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 23 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Table 22: RAM Cell Synchronous & Asynchronous Read Timing Value (ns) Symbol tSRA tHRA tSRE tHRE tRCRD Parameter: RAM Cell Synchronous Read Timing Min RA setup time to RCLK: time the Read ADDRESS must be stable before the active edge of the Read CLOCK RA hold time to RCLK: time the Read ADDRESS must be stable after the active edge of the Read CLOCK RE setup time to WCLK: time the Read ENABLE must be stable before the active edge of the Read CLOCK RE hold time to WCLK: time the Read ENABLE must be stable after the active edge of the Read CLOCK RCLK to RD: time between the active Read CLOCK edge and the time when the data is available at RD RAM Cell Asynchronous Read Timing rPDRD RA to RD: time between when the Read ADDRESS is input and when the DATA is output 2.06 0.686 0 0.243 0 Max 4.38 24 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C t t IN , t INI ICLK t ISU + t SID QE R D PAD Figure 15: Input Register Cell Table 23: Input Register Cell Value (ns) Symbol tISU tIHL tICLK tIRST tIESU tIEH Parameter: Input Cell Register Only Min Input register setup time: time the synchronous input of the flip flop must be stable before the active clock edge Input register hold time: time the synchronous input of the flip flop must be stable after the active clock edge Input register clock to out: time taken by the flip flop to output after the active clock edge Input register reset delay: time between when the flip flop is "reset"(low) and when the output is consequently "reset" (low) Input register clock enable setup time: time "enable" must be stable before the active clock edge Input register clock enable hold time: time "enable" must be stable after the active clock edge 3.12 0 0.37 0 Max 1.08 0.99 - (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 25 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C R CLK D tISU tIHL tICLK tIRST Q E t IESU tIEH Figure 16: Input Register Cell Timings Table 24: Standard Input Delays Symbol Standard Input Delays tSID(LVTTL) tSID(LVCMOS2) tSID(GTL+) tSID(SSTL3) tSID(SSTL2) Parameter To get the total input delay add this delay to tISU LVTTL input delay: Low Voltage TTL for 3.3V applications LVCMOS2 input delay: Low Voltage CMOS for 2.5V and lower applications GTL+ input delay: Gunning Transceiver Logic SSTL3 input delay: Stub Series Terminated Logic for 3.3V SSTL2 input delay: Stub Series Terminated Logic for 2.5V Value (ns) Min Max 0.34 0.42 0.68 0.55 0.61 26 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Quad net Figure 17: Global Clock Structure Table 25: Clock Delay Clock Performance Clock Logic Cells (Internal) I/O's (External) Parameters Global Clock signal generated internally Clock signal generated externally 1.51 ns (max) 2.06 ns (max) Dedicated n/a 1.73 ns (max) Table 26: Eclipse Global Clock Performance Value (ns) Clock Segment tPGCK tBGCK Parameter Min Global clock pin delay to quad net Global clock buffer delay (quad net to flip flop) Max 1.34 0.56 Programmable Clock External Clock Global Clock Buffer Global Clock tPGCK tBGCK Figure 18: Global Clock Structure Schematic (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 27 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Table 27: Output Register Cell Symbol tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ tCOP Parameter: Output Register Cell Only Output Delay low to high (90% of H) Output Delay high to low (10% of L) Output Delay tri-state to high (90% of H) Output Delay tri-state to low (10% of L) Output Delay high to tri-State Output Delay low to tri-State Clock to out delay (does not include clock tree delays) Min Max 0.40 0.55 2.94 2.34 3.07 2.53 3.15 (fast slew) 10.2 (slow slew) PAD OUTPUT REGISTER Figure 19: Output Register Cell 28 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C H L H Z L H Z L tOUTLH tPZH H L H Z L H Z L tPLZ tOUTHL tPZL tPHZ Figure 20: Output Register Cell Timing Table 28: Output Slew Rates @ VCCIO = 3.3 V Fast Slew Rising Edge Falling Edge 2.8 V/ns 2.86 V/ns Slow Slew 1.0 V/ns 1.0 V/ns Table 29: Output Slew Rates @ VCCIO = 2.5 V Fast Slew Rising Edge Falling Edge 1.7 V/ns 1.9 V/ns Slow Slew 0.6 V/ns 0.6 V/ns tPHZ 1K Ohms 5pF 1K Ohms tPLZ 5pF Figure 21: Loads for tPXZ (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 29 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Pin Type Descriptions The QL6432 Device Pins are indicated in Table 30. Some of the pins presented in this table connect to the PCI bus, and others are programmable as user I/O. Table 30: Pin Descriptions Pin TDI/RSI TRSTB/RRO TMS TCK TDO/RCO I/GCLK I/O VCC VCCIO 30 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Recommended Unused Pin Terminations All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally using the Configuration Editor. This option is given in the bottom-right corner of the placement window. To use the Placement Editor, choose Constraint Fix Placement in the Option pulldown menu of SpDE. The rest of the pins should be terminated at the board level in the manner presented in Table 31. Table 31: Recommended Unused Pin Terminations Signal Name PLLOUT NOTE: x -> number, y -> alphabetical character. (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 31 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C 208 PQFP Pinout Diagram Top QuickPCI QL5632-33BPQ208C 32 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C 208 PQFP Pinout Table Table 32: 208 PQFP Pinout Table 208 PQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Function PLLRST(3) VCCPLL(3) GND GND AD [8] CBEN [0] AD [7] VCCIO(A) AD [6] AD [5] IOCTRL(A) VCC INREF(A) IOCTRL(A) AD [4] AD [3] AD [2] AD [1] VCCIO(A) AD [0] GND IO(A) TDI CLK(0) CLK(1) VCC CLK(2),PLLIN(2) CLK(3),PLLIN(1) VCC CLK(4),DEDCLK, PLLIN(0) IO(B) IO(B) GND VCCIO(B) IO(B) 208 PQFP 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Function IO(B) IO(B) IO(B) IOCTRL(B) INREF(B) IOCTRL(B) IO(B) IO(B) VCCIO(B) IO(B) VCC IO(B) IO(B) GND TDO PLLOUT(1) GNDPLL(2) GND VCCPLL(2) PLLRST(2) VCC IO(C) GND IO(C) VCCIO(C) IO(C) IO(C) IO(C) IO(C) IO(C) IO(C) IOCTRL(C) INREF(C) IOCTRL(C) IO(C) 208 PQFP 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Function IO(C) VCCIO(C) IO(C) IO(C) GND VCC IO(C) TRSTB VCC IO(D) IO(D) IO(D) GND VCCIO(D) IO(D) VCC IO(D) IO(D) VCC IO(D) IO(D) IOCTRL(D) INREF(D) IOCTRL(D) IO(D) IO(D) IO(D) VCCIO(D) IO(D) IO(D) GND PLLOUT(0) GND GNDPLL(1) PLLRST(1) 208 PQFP 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Function VCCPLL(1) IO(E) GND IO(E) IO(E) VCCIO(E) IO(E) VCC IO(E) IO(E) IO(E) IOCTRL(E) INREF(E) IOCTRL(E) IO(E) IO(E) VCCIO(E) GND IO(E) IO(E) IO(E) CLK(5),PLLIN(3) CLK(6) VCC CLK(7) VCC CLK TMS IO(F) RSTN GNTN GND VCCIO(F) REQN AD [31] 208 PQFP 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 Function AD [30] AD [29] AD [28] IOCTRL(F) INREF(F) VCC IOCTRL(F) AD [27] AD [26] VCCIO(F) AD [25] AD [24] GND CBEN [3] PLLOUT(3) GNDPLL(0) GND VCCPLL(0) PLLRST(0) GND IDSEL VCCIO(G) AD [23] AD [22] VCC AD [21] AD [20] AD [19] IOCTRL(G) INREF(G) IOCTRL(G) AD [18] AD [17] AD [16] VCC 208 PQFP 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Function CBEN [2] VCCIO(G) GND FRAMEN IRDYN TRDYN VCC TCK VCC DEVSELN STOPN PERRN GND VCCIO(H) SERRN PAR IOCTRL(H) CBEN [1] INREF(H) VCC IOCTRL(H) AD [15] AD [14] AD [13] AD [12] AD [11] AD [10] VCCIO(H) GND AD [9] PLLOUT(2) GND GNDPLL(3) VCCIO(A), VCCIO(F), VCCIO(G) and VCCIO(H) must be connected to VCCIO(PCI) (3.3 V). Summary: 49 PCI pins, 51 user I/O, and 8 GCLK. (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 33 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C 208 PQFP Packaging Drawing 34 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C 280 LFBGA Pinout Diagram Top QuickPCI QL5632-33BPT280C Bottom 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIN A1 CORNER A B C D E F G H J K L M N P R T U V W (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 35 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C 280 LFBGA Pinout Table Table 33: 280 LFBGA Pinout Table 280 LFBGA A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 C7 C8 C9 Function PLLOUT(3) GNDPLL(0) AD [18] AD [20] IDSEL IOCTRL(F) AD [26] AD [30] RSTN CLK(7) I/O(E) I/O(E) I/O(E) IOCTRL(E) I/O(E) I/O(E) I/O(E) PLLRST(1) GND PLLRST(0) GND AD [19] AD [21] CBEN [3] INREF(F) AD [27] AD [31] TMS CLK(6) I/O(E) I/O(E) IOCTRL(E) I/O(E) I/O(E) I/O(E) VCCPLL(1) GNDPLL(1) PLLOUT(0) CBEN [2] VCCPLL(0) AD [17] AD [22] VCCIO(F) IOCTRL(F) AD[28] REQN VCCIO(F) 280 LFBGA C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 Function CLK(5)/PLLIN(3) VCCIO(E) I/O(E) I/O(E) I/O(E) VCCIO(E) I/O(E) I/O(E) I/O(E) I/O(E) TRDYN IRDYN AD [16] AD [23] AD [24] AD [25] AD [29] GNTN CLK I/O(E) I/O(E) I/O(E) INREF(E) I/O(E) I/O(E) I/O(D) I/O(D) I/O(D) I/O(D) PERRN STOPN VCCIO(G) FRAMEN GND VCC VCC VCC VCC GND GND VCC VCC GND GND I/O(D) VCCIO(D) INREF(D) 280 LFBGA E19 F1 F2 F3 F4 F5 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 G15 G16 G17 G18 G19 H1 H2 H3 H4 H5 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J15 J16 J17 J18 J19 K1 K2 K3 K4 K5 K15 Function IOCTRL(D) INREF(G) IOCTRL(G) SERRN DEVSELN GND VCC IOCTRL(D) I/O(D) I/O(D) I/O(D) AD [14] AD [15] IOCTRL(G) PAR VCC VCC I/O(D) I/O(D) I/O(D) I/O(D) AD [11] AD [12] AD [13] I/O(G) CBEN [1] VCC VCC I/O(D) I/O(D) I/O(D) AD [8] AD [9] VCCIO(G) AD [10] GND VCC I/O(C) VCCIO(D) I/O(D) I/O(D) VCC TCK AD [7] CBEN [0] GND GND 280 LFBGA K16 K17 K18 K19 L1 L2 L3 L4 L5 L15 L16 L17 L18 L19 M1 M2 M3 M4 M5 M15 M16 M17 M18 M19 N1 N2 N3 N4 N5 N15 N16 N17 N18 N19 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 R1 R2 R3 Function I/O(C) I/O(D) I/O(C) TRSTB AD [4] AD [5] VCCIO(H) AD [6] VCC GND I/O(C) VCCIO(C) I/O(C) I/O(C) AD [0] AD [1] AD [2] AD [3] VCC VCC INREF(C) I/O(C) I/O(C) I/O(C) IOCTRL(H) I/O(H) I/O(H) I/O(H) VCC VCC I/O(C) I/O(C) IOCTRL(C) IOCTRL(C) I/O(H) I/O(H) IOCTRL(H) INREF(H) VCC GND I/O(C) I/O(C) I/O(C) I/O(C) I/O(H) I/O(H) VCCIO(H) 280 LFBGA R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 Function I/O(H) GND GND VCC VCC GND GND VCC VCC VCC VCC GND I/O(C) VCCIO(C) I/O(C) I/O(C) I/O(H) I/O(H) I/O(A) I/O(A) I/O(A) IOCTRL(A) I/O(A) I/O(A) I/O(A) I/O(A) CLK(3)/PLLIN(1) I/O(B) I/O(B) I/O(B) I/O(B) I/O(B) VCCPLL(2) I/O(B) I/O(B) I/O(A) I/O(A) VCCPLL(3) I/O(A) VCCIO(A) INREF(A) I/O(A) I/O(A) VCCIO(A) CLK(0) VCCIO(B) I/O(B) 280 LFBGA U13 U14 U15 U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 Function I/O(B) IOCTRL(B) VCCIO(B) I/O(B) TDO PLLRST(2) I/O(B) PLLOUT(2) GNDPLL(3) GND I/O(A) I/O(A) IOCTRL(A) I/O(A) I/O(A) I/O(A) CLK(1) CLK(4)DEDCLK/ PLLIN(0) I/O(B) I/O(B) INREF(B) I/O(B) I/O(B) I/O(B) GNDPLL(2) GND GND PLLRST(3) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) I/O(A) TDI CLK(2)/PLLIN(2) I/O(B) I/O(B) I/O(B) IOCTRL(B) I/O(B) I/O(B) I/O(B) I/O(B) PLLOUT(1) VCCIO(F), VCCIO(G) and VCCIO(H) must be connected to VCCIO(PCI) (3.3 V). Summary: 49 PCI pins, 115 user I/O, and 8 GCLK. 36 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C 280 LFBGA Packaging Drawing (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 37 QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Ordering Information QL 5632 - 33B - PQ208 C QuickLogic device Operating Range C = Commercial I = Industrial M = Military Package Code PQ208 = 208-pin PQFP PT280 = 280-ball LFBGA QuickPCI device part number Speed Grade 33B = 33 MHz PCI bus Revision History Revision Rev. A Rev. B Date August 2002 January 2003 Originator and Comments Bernhard Andretzky, Stacy Joseph, Andreea Rotaru and Paul Micallef Bernhard Andretzky and Andreea Rotaru Rev. C Bernhard Andretzky and Kathleen Murchek Updated Figure 1. QL5632 Block Diagram. Changed D.S. Supply Current to Quiescent Current. Changed TA ambient temperature to September 2003 TJ junction temperature and deleted TC case temperature. Updated pinout diagrams package drawings, and tables. Updated contact and trademark information. Contact Information Telephone: (408) 990 4000 (US) (416) 497 8884 (Canada) +(44) 1932 57 9011 (Rest of Europe) +(49) 89 930 86 170 (Germany & Benelux) +(8621) 2890 3029 (Asia) +(81) 45 470 5525 (Japan) E-mail: Support: Web site: info@quicklogic.com http://www.quicklogic.com/support http://www.quicklogic.com/ 38 * www.quicklogic.com * * * * * (c) 2003 QuickLogic Corporation QL5632 Enhanced QuickPCI Device Data Sheet Rev. C Copyright and Trademark Information Copyright (c) 2003 QuickLogic Corporation. All Rights Reserved. The information contained in this document and the accompanying software programs is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic and the QuickLogic logo, pASIC, ViaLink, DeskFab, QuickRAM, QuickPCI and QuickWorks are registered trademarks of QuickLogic Corporation; Eclipse, EclipsePlus, Eclipse II, QuickDR, QuickTools, QuickCore, QuickPro, SpDE, WebASIC, and WebESP are trademarks of QuickLogic Corporation. (c) 2003 QuickLogic Corporation www.quicklogic.com * * * * * * 39 |
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